Semiconductor device and method for manufacturing the same

ABSTRACT

A semiconductor device having power supply leads and signal leads on the main surface of a semiconductor chip. Since floating capacitance applied to the power supply leads can be made large and floating capacitance applied to the signal leads can be made small by making the interval between the signal leads and the semiconductor chip larger than the interval between the power supply leads and the semiconductor chip, the prevention of fluctuations in power source potential and the acceleration of the signal propagation speed can be carried out at the same time. As a result, the electric characteristics of the semiconductor device can be improved.

TECHNICAL FIELD

The present invention relates to a semiconductor device and,particularly, to an effective technology for application in asemiconductor device having signal leads and power supply leads on asemiconductor chip.

BACKGROUND ART

There is available a semiconductor device in which a semiconductor chiphaving a circuit system mounted there on is sealed with a resin sealer.In this semiconductor device, the die pad (also called “tub”) of a leadframe is omitted and an LOC (Lead On Chip) structure or a COL (Chip OnLead) structure which can be used for large-sized chips is employed. AnLOC structure semiconductor device is disclosed by Japanese PatentLaid-open No. Hei 2-246125 (laid open on Oct. 1, 1990), for example. ACOL structure semiconductor device is disclosed by Thesis No. ICD 89-103of the technical research report of the Denshi Joho Tsushin Gakkaipublished in March, 1989.

The above LOC structure semiconductor device is constituted such thatleads are fixed on the main surface (circuit formed surface) of asemiconductor chip through an insulating film. The insulating film hasan adhesive layer formed of a polyimide-based resin on both sides (frontand rear sides) of a resin substrate made from a polyimide-based resin.Since this insulating film easily absorbs water, water absorbed by theinsulating film is vaporized and expanded with heat at the time of atemperature cycle test which is an environment test for a semiconductordevice and heat when a semiconductor device is mounted, thereby causingthe cracking of a resin sealer (package cracking).

An attempt is then made to arrange leads on the main surface of asemiconductor chip by eliminating the insulating film. This technologyis disclosed by Japanese Patent Laid-open No. Hei 8-274234 (laid open onOct. 18, 1996), for example.

A semiconductor chip having a circuit system mounted thereon has such astructure that a multi-layer wiring layer which consists of a pluralityof wiring layers and a plurality of interlayer insulating layers isformed on a semiconductor substrate and a surface protective film (finalprotective film) is formed on the multi-layer wiring layer. Power sourcewires for supplying an operation potential (Vcc) and a referencepotential (Vss) to transistor elements constituting the circuit systemare formed in each wiring layer of the multi-layer wiring layer.Further, signal wires for connecting the transistor elements are formedin each wiring layer. The power source wires and the signal wires areelectrically connected to respective external terminals for power sourceand respective external terminals for signals formed on the uppermostwiring layer of the multi-layer wiring layer.

Meanwhile, power supply leads electrically connected to the externalterminals for power source by wires and signal leads electricallyconnected to the external terminals for signals by wires are formed onthe main surface of the semiconductor chip. Floating capacitance(parasitic capacitance) is applied to the power supply leads and thesignal leads because the power supply leads and the signal leads areformed on the power source wires formed in the multi-layer wiring layerof the semiconductor chip through the surface protective film and aninsulator such as the insulating film. Floating capacitance applied tothe power supply leads is preferably large in order to preventfluctuations in power source potential caused by switching noise.Parasitic capacitance applied to the signal leads is preferably small inorder to increase the signal propagation speed.

However, as the power supply leads and the signal leads are situated onthe same plane on the main surface of the semiconductor chip, floatingcapacitance applied to the power supply leads and floating capacitanceapplied to the signal leads are the same, whereby the prevention offluctuations in power source potential and the acceleration of thesignal propagation speed cannot be carried out at the same time, therebypreventing improvement on the electric characteristics of thesemiconductor device. Particularly when the insulating film iseliminated and leads are fixed on the main surface of the semiconductorchip through an adhesive material, floating capacitance applied to thepower supply leads and the signal leads become large, which is preferredfor the prevention of fluctuations in power source potential but notpreferred for the acceleration of the signal propagation speed.

It is an object of the present invention to provide a technology whichcan improve the electric characteristics of a semiconductor device.

The above and other objects and new features of the present inventionwill become apparent from the following description when taken intoconjunction with the accompanying drawings.

DISCLOSURE OF THE INVENTION

Overviews of representatives of the present invention disclosed in thisspecification are described briefly as follows.

(1) There is provided a semiconductor device having power supply leadsand signal leads on the main surface of a semiconductor chip, whereinthe interval between the signal leads and the semiconductor chip is madelarger than the interval between the power supply leads and thesemiconductor chip. The signal leads are separated from thesemiconductor chip and the power supply leads are fixed to the mainsurface of the semiconductor chip. Further, the power supply leads arefixed to the main surface of the semiconductor chip directly or throughan adhesive layer.

A surface protective film is formed on the main surface of thesemiconductor chip and power source wires electrically connected to thepower supply leads are formed under the surface protective layer.

The power supply leads and the signal leads are electrically connectedto respective external terminals arranged on the main surface of thesemiconductor chip, the semiconductor chip, the inner portions (innerleads) of the power supply leads, the inner portions of the signal leadsand the wires are sealed by a resin sealer, and the outer portions(outer leads) of the power supply leads and the signal leads are drawnoutside the resin sealer.

(2) There is provided a semiconductor device comprising:

a rectangular semiconductor chip having a plurality of semiconductorelements and a plurality of external terminals on the main surface, theplurality of external terminals being arranged in a longitudinaldirection;

first leads and second leads, each having inner portions and outerportions, parts of the inner portions being arranged on the main surfaceof the semiconductor chip, and the end portions of the inner portionsbeing arranged near the plurality of external terminals and electricallyconnected to the plurality of external terminals; and

a rectangular resin sealer for sealing the semiconductor chip and theinner portions of the first leads and the second leads, whose long sidesextend along the long sides of the semiconductor chip and whose shortsides extend along the short sides of the semiconductor chip, wherein

the outer portions of the first leads and the second leads project fromthe long sides of the resin sealer;

the inner portions of the first leads and the second leads extend overthe short sides of the semiconductor chip and lie on the main surface ofthe semiconductor chip;

the distance between parts of the inner portions of the second leadslying on the main surface of the semiconductor chip and the main surfaceof the semiconductor chip is larger than the distance between parts ofthe inner portions of the first leads lying on the main surface of thesemiconductor chip and the main surface of the semiconductor chip; and

the first leads are connected to fixed potential terminals out of theplurality of external terminals and the second leads are connected tosignal terminals out of the plurality of external terminals.

Since floating capacitance applied to the power supply leads can be madelarge and floating capacitance applied to the signal leads can be madesmall by the above means, the prevention of fluctuations in power sourcepotential and the acceleration of the signal propagation speed can becarried out at the same time. As a result, the electric characteristicsof a semiconductor device can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a semiconductor device according to anembodiment of the present invention from which a top portion of a resinsealer is removed;

FIG. 2 is an enlarged plan view of key parts of FIG. 1;

FIG. 3 is a sectional view of the above semiconductor device cut on lineA—A′ of FIG. 2;

FIG. 4 is a enlarged sectional view of key parts of FIG. 3;

FIG. 5 is a sectional view of key parts showing the schematicconstitution of a semiconductor chip mounted on the above semiconductordevice;

FIG. 6 is a plan view of a lead frame used in the production of theabove semiconductor device;

FIG. 7 is a sectional view of key parts for explaining the method ofmanufacturing the above semiconductor device;

FIG. 8 is a plan view of a semiconductor device as a first modificationof the above embodiment of the present invention from which a topportion of a resin sealer is removed;

FIG. 9 is a plan view of a semiconductor device as a second modificationof the above embodiment of the present invention from which a topportion of a resin sealer is removed;

FIG. 10 is a plan view of a semiconductor device as a third modificationof the above embodiment of the present invention from which a topportion of a resin sealer is removed; and

FIG. 11 is a sectional view of the semiconductor device as the thirdmodification of the above embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The constitution of the present invention will be described hereinunderwith reference to an embodiment.

Elements having the same functions are given the same reference symbolsin all the figures for explaining the embodiment and their descriptionsare not repeated.

A semiconductor device according to an embodiment of the presentinvention has an LOC structure that a plurality of leads 2 are formed onthe main surface (circuit formed surface) of a semiconductor chip 1 asshown in FIGS. 1, 2 and 3.

The plane shape of the semiconductor chip 1 is not limited to this butis formed rectangular, for example. This semiconductor chip 1 has, forexample, a DRAM (Dynamic Random Access Memory) mounted thereon as acircuit system. In the center area of the main surface of thesemiconductor chip 1, a plurality of external terminals (bonding pads)BP are arranged in the longitudinal direction of the center region.

The plurality of leads 2 are electrically connected to the plurality ofexternal terminals (bonding pads) BP arranged on the main surface of thesemiconductor chip 1 by wires 4, respectively. The wires 4 are, forexample, gold (Au) wires. The wires 4 may be, for example, aluminum (Al)wires, copper (Cu) wires, metal wires coated with an insulating resin onthe surface, or the like . The wires 4 are connected by a bonding methodmaking use of thermal press bonding and ultrasonic vibration.

The semiconductor chip 1, the inner portions (inner leads) of theplurality of leads 2, the wires 4 and the like are sealed by a resinsealer 5. The resin sealer 5 is made from, for example, a biphenyl-basedresin containing a phenol-based curing agent, silicone rubber, fillerand the like in order to reduce stress. The resin sealer 5 is formed by,for example, a transfer molding method which is suitable formass-production. The transfer molding method uses a metal mold having apot, runner, inflow gate, cavity and the like to form a resin sealer byinjecting a resin into the cavity from the pot through the runner andthe inflow gate by pressure. The plane shape of the resin sealer 5 isnot limited to this but is rectangular, for example.

The outer portions (outer leads) of the plurality of leads 2 are laidfrom the resin sealer 5 to the outside of the resin sealer 5 and bentlike letter J. The outer portions of the plurality of leads 2 are formedby disconnecting them from the frame body of a lead frame after theresin sealer 5 is formed and molding them into a predetermined shape inthe production process of a semiconductor device.

Support leads 6 are arranged outside the two opposed short sides of thesemiconductor chip 1. The support leads 6 are sealed by the resin sealer5 together with the semiconductor chip 1, the inner portions of theplurality of leads 2 and the wires 4. The support leads 6 are used tosupport the resin sealer 5 in the frame body of the lead frame in theproduction process of a semiconductor device.

The plurality of leads 2 are divided into two groups. The leads 2 of onegroup are mainly arranged on the side of one of the two opposed longsides of the semiconductor chip 1. The leads 2 of the other group aremainly arranged on the side of the other long side of the semiconductorchip 1. One ends of the leads 2 of one group are disposed in thearrangement direction of the external terminals BP of the semiconductorchip 1 and the other ends are disposed along one of the long sides ofthe resin sealer 5 which faces one of the long sides of thesemiconductor chip 1. One ends of the leads 2 of the other group aredisposed in the arrangement direction of the external terminals BP ofthe semiconductor chip 1 and the other ends are disposed along the otherlong side of the resin sealer 5 which faces the other long side of thesemiconductor chip 1. That is, the semiconductor device of thisembodiment is not limited to this but has a two-direction lead layoutstructure.

Four out of the plurality of leads 2 are used as power supply leads 2Aand the other leads are used as signal leads 2B. That is, the powersupply leads 2A and the signal leads 2B are arranged on the main surfaceof the semiconductor chip 1. In FIG. 1, the power supply leads 2A andthe signal leads 2B are each given terminal names. Vcc terminals areoperational potential terminals whose power source potential is fixed toan operational potential (for example, 5 V). Vss terminals are referencevoltage potential terminals whose power source potential is fixed to areference potential (for example 0 V) I/01 to I/04 are data input/outputterminals. A1 to A11 terminals are address input terminals. A RAS barterminal is a low address strobe terminal. A CAS bar terminal is acolumn address strobe terminal. A WE bar terminal is a read/write enableterminal. An OE bar terminal is an output enable terminal.

The above semiconductor chip 1 is mainly composed of a p typesemiconductor substrate 10 made from monocrystal silicon, for example,as shown in FIG. 5. A p type well region 12 is formed in the elementforming region of the p type semiconductor substrate 10, and a MISFET(Metal Insulator Semiconductor Field Effect Transistor) Q constitutingthe peripheral circuit of a DRAM is formed in this p type well region12. A field insulating film 11 is formed in the element separatingregion of the p type semiconductor substrate 10.

The above MISFET Q is mainly composed of the p type well region 12 whichis a channel forming region, a gate insulating film, gate electrodes 13and a pair of n type semiconductor regions 14 which are a source regionand a drain region. The pair of n type semiconductor regions 14 areelectrically connected to wires 16 formed of a first wiring layerthrough connection holes formed in the interlayer insulating film 15.The wires 16 are electrically connected to wires 18 formed of a secondwiring layer through connection holes formed in the interlayerinsulating film 17. The wires 18 are electrically connected to wires 20formed of a third wiring layer through connection holes formed in theinterlayer insulating film 17. The wires 20 are covered with a surfaceprotective film (final protective film) 21. That is, the semiconductorchip 1 has a multi-layer wiring layer consisting of a plurality ofwiring layers and a plurality of interlayer insulating layers formed onthe semiconductor substrate 10 and the surface protective film 21 formedon the multi-layer wiring layer. The main surface of the semiconductorchip 1 is formed of the surface protective film 21. The surfaceprotective film 21 is a laminate film comprising a silicon nitride filmand a polyimide-based resin film (specifically, a polyimide isoindolequinazoline dione resin film) in order to improve the moistureresistance and α-ray resisting strength of a DRAM. The silicon nitridefilm is formed by plasma CVD (Chemical Vapor Deposition), for example,and the polyimide-based resin film is formed by rotation coating, forexample. The above external terminals BP are formed on the uppermostwiring layer of the multi-layer wiring layer.

Power source wires (20, 18, 16) for supplying an operational potential(Vcc) and a reference potential (Vss) to the MISFET's Q included in theperipheral circuit of the DRAM are formed in the respective wiringlayers of the multi-layer wiring layer of the semiconductor chip 1.Signal wires (20, 18, 16) for connecting the MISFET's Q are formed inthe respective wiring layers of the multi-layer wiring layer. The powersource wires are electrically connected to the external terminals forpower source out of the external terminals BP arranged on the mainsurface of the semiconductor chip 1, and the external terminals forpower source are electrically connected to the power supply leads 2A bythe wires 4. The signal wires are electrically connected to the externalterminals for signals out of the external terminals BP arranged on themain surface of the semiconductor chip 1, and the external terminals forsignals are electrically connected to the signal leads 2B by the wires4.

As shown in FIG. 3, each of the power supply leads 2A is formed suchthat the end portion of the inner portion are located on thesemiconductor chip 1 side unlike the other portions. Similarly, each ofthe signal leads 2B is formed such that the end of the inner portion islocated on the semiconductor chip 1 side unlike the other portions.

The end portion of the inner portion of the power supply lead 2A isbonded and fixed to the main surface of the semiconductor chip 1 throughan adhesive layer 3, and the other portion of the inner portion isseparated from the main surface of the semiconductor chip 1. Theadhesive layer 3 and the resin of the resin sealer 5 are interposedbetween the inner portion of the power supply lead 2A and thesemiconductor chip 1. The adhesive layer 3 is formed of apolyimide-based thermosetting resin, for example. In FIG. 1 and FIG. 2,the fixed area of the power supply lead 2A is shown by slant lines tomake these figures more understandable.

The end portion and other portion of the inner portion of the signallead 2B are separated from the main surface of the semiconductor chip 1in the region of the semiconductor chip 1. The resin of the resin sealer5 is interposed between the inner portion of the signal lead 2A and themain surface of the semiconductor chip 1.

As shown in FIG. 4, the interval L2 between the end portion of the innerportion of the signal lead 2B and the semiconductor chip 1 is largerthan the interval L1 between the end portion of the inner portion of thepower supply lead 2A and the semiconductor chip 1. That is, the endportion of the signal lead 2B is located farther from the main surfaceof the semiconductor chip 1 than the end portion of the power supplylead 2B. The interval L2 is set to about 50 to 60 μm and the interval L1is set to about 5 to 10 μm.

The inner portions of the power supply leads 2A and the signal leads 2Bare arranged on the main surface of the semiconductor chip 1. Thesemiconductor chip 1 has a multi-layer wiring layer consisting of aplurality of wiring layers and a plurality of interlayer insulatinglayers formed on the semiconductor substrate 1 and the surfaceprotective film 21 formed on the multi-layer wiring layer as describedabove. That is, the inner portions of the power supply leads 2A areformed on the power source wires formed in the multi-layer wiring layerof the semiconductor chip 1 through the surface protective layer 21, theadhesive layer 3 and an insulator such as the resin of the resin sealer5, and the inner portions of the signal leads 2B are formed on the powersource wires formed in the multi-layer wiring layer of the semiconductorchip 1 through the surface protective film 21 and an insulator such asthe resin of the resin sealer 5. Therefore, floating capacitance(parasitic capacitance) is applied to the power supply leads 2A and thesignal leads 2B. Floating capacitance applied to the power supply leads2A is preferably large in order to prevent fluctuations in power sourcepotential caused by switching noise. Floating capacitance applied to thesignal leads 2B is preferably small in order to increase the signalpropagation speed.

Floating capacitance applied to the signal leads 2B is smaller thanfloating capacitance applied to the power supply leads 2A because theinterval L2 between the end portions of the inner portions of the signalleads 2B and the semiconductor chip 1 is made larger than the intervalL1 between the end portions of the inner portions of the power supplyleads 2A and the semiconductor chip 1. That is, floating capacitanceapplied to the power supply leads 2A can be made large and floatingcapacitance applied to the signal leads 2B can be made small by makingthe interval L2 between the end portions of the inner portions of thesignal leads 2B and the semiconductor chip 1 larger than the interval L1between the end portions of the inner portions of the power supply leads2A and the semiconductor chip 1.

As shown in FIG. 1, the end portions of the four power supply leads 2Aare disposed near the respective corner portions of the semiconductorchip 1 and bonded and fixed to the main surface of the semiconductorchip 1 through the adhesive layer 3. That is, the semiconductor chip 1is supported by the four power supply leads 2A in the production processof the semiconductor device.

Each of the inner portions of the power supply leads 2A extends over theshort side of the semiconductor chip 1, a part thereof lies on the mainsurface of the semiconductor chip 1 and the other part thereof liesoutside the periphery of the semiconductor chip 1.

Out of the plurality of signal leads 2B, the inner portions of signalleads 2B used as I/O1 to I/04 terminals and signal leads 2B used as A2to A4 terminals extend over the short sides of the semiconductor chip 1and parts thereof lie on the main surface of the semiconductor chip 1and the other parts lie outside the periphery of the semiconductor chip1. Out of the plurality of signal leads 2B, the inner portions of signalleads 2B used as A0 and A1 terminals and A5 to A11 terminals, a signallead 2B used as a RAS bar terminal, a signal lead 2B used as a CAS barterminal, a signal lead 2B used as a WE bar terminal and a signal lead2B used as an OE bar terminal extend over the short sides of thesemiconductor chip 1, parts thereof lie on the main surface of thesemiconductor chip 1 and the other parts thereof lie outside theperiphery of the semiconductor chip 1.

Since the external terminals BP arranged in the center region of themain surface of the semiconductor chip 1 are arranged along the longsides of the semiconductor chip 1, the leading portions lying on themain surface of the semiconductor chip 1 of the signal leads 2Bextending over the short sides of the semiconductor chip 1 must be drawnaround on the main surface to the semiconductor chip 1 compared with thesignal leads 2B extending over the long sides of the semiconductor chip1, thereby increasing their areas opposite to the main surface of thesemiconductor chip 1. Therefore, as floating capacitance between thechip and the leads applied to the signal leads 2B becomes large, atleast the distance between the signal leads 2B extending over the shortsides of the semiconductor chip 1 and the main surface of thesemiconductor chip 1 (distance between the chip and the leads) must bemade large.

The bending (offsetting) of the signal leads 2B and the power supplyleads 2A extending over the short sides of the semiconductor chip 1 iscarried out on the leading portions extending linearly. The bending ofthe signal leads 2B extending over the long sides of the semiconductorchip 1 is also carried out on the leading portions extending linearly.The reason for this is that it is difficult to bend (offset) close leadswhich do not extend linearly. Therefore, as shown in FIG. 1, FIG. 2 andFIG. 3, the bent portions of the power supply leads 2A extending overthe short sides of the semiconductor chip 1 and the bent portions of thesignal leads 2B extending over the long sides of the semiconductor chip1 differ from one another in location.

The semiconductor device constituted as described above is formed by aproduction process using a lead frame LF shown in FIG. 6.

The lead frame LF has a plurality of leads 2 and two support leads 6 ina region specified by a frame body 7. The plurality of leads 2 aresupported by the frame body 7 and connected to one another by tie bars(dam bars) 8. The two support leads 6 are supported by the frame body 7.The leads 2 and the support leads 6 are integrated with the frame body7.

Each of the plurality of leads 2 consists of an inner portion sealed bythe resin sealer 5 and an outer portion drawn to the outside of theresin sealer 5. The end portion of the inner portion is bent such thatit is located lower than the other portion in a thickness direction ofthe device.

The lead frame LF is made from an iron (Fe)-nickel (Ni) based alloy,copper or copper alloy. This lead frame is formed by etching or pressinga plate material to form a predetermined lead pattern and pressing theend portions of the leads 2.

Out of the plurality of leads 2, the end portions of the inner portionsof the power supply leads 2A are located lower than the end portions ofthe inner portions of the signal leads 2B in the thickness direction ofthe frame. That is, the end portions of the inner portions of the powersupply leads 2A are greatly offset so that they become closer to themain surface of the semiconductor chip 1 than the end portions of theinner portions of the signal leads 2B.

A description is subsequently given of the method of producing the abovesemiconductor device with reference to FIG. 7.

The lead frame LF shown in FIG. 6 is first prepared.

Then, out of the plurality of leads 2 supported by the frame body 7 ofthe lead frame LF, the adhesive layer 3 is formed on the end portions ofthe inner portions of the four power supply leads 2A. The adhesive layer3 is formed by coating, for example, a polyimide-based thermosettingresin on the chip fixing surface side of the end portions of the powersupply leads 2A with a dispenser.

Thereafter, the power supply leads 2A of the lead frame LF are bondedand fixed to the main surface of the semiconductor chip 1 through theadhesive layer 3 to fix the lead frame LF to the semiconductor chip 1.The power supply leads 2A are fixed by press bonding under heating. Inthis step, the signal leads 2B of the lead frame LF are arranged awayfrom the main surface of the semiconductor chip 1. The above steps areshown in FIG. 7(A).

The external terminals (BP) arranged on the main surface of thesemiconductor chip 1 are electrically connected to the leads 2 of thelead frame LF by the wires 4. Out of the leads 2, the power supply leads2A are electrically connected to the external terminals for power sourceand the signal leads 2B are electrically connected to the externalterminals for signals. The wires 4 are connected by a bonding methodmaking use of thermal press bonding and ultrasonic vibration. In thisstep, the connection of the signal leads 2B and the wires 4 is carriedout while the end portions of the signal leads 2B are fixed to the mainsurface of the semiconductor chip 1 with a lead holding jig. The abovesteps are shown in FIG. 7(B).

Thereafter, the lead frame LF is placed between the upper mold and lowermold of a metal mold, and the semiconductor chip 1, the inner portionsof the leads 2 and the support leads 6 are arranged in the cavity of themetal mold. The metal mold has a pot, runner, inflow gate and the likebesides the cavity. In this step, the interval (L2) between the signalleads 2B and the semiconductor chip 1 is made larger than the interval(L1) between the power supply leads 2A and the semiconductor chip 1, thesignal leads 2B are separated from the semiconductor chip 1, and thepower supply leads 2A are fixed to the semiconductor chip 1.

A resin is injected into the cavity from the pot of the metal moldthrough the runner and the inflow gate by pressure, and while theinterval (L2) between the signal leads 2B and the semiconductor chip 1is larger than the interval (L1) between the power supply leads 2A andthe semiconductor chip 1, the signal leads 2B are apart from thesemiconductor chip 1, and the power supply leads 2A are fixed to thesemiconductor chip 1, the semiconductor chip 1, the inner portions ofthe power supply leads 2A, the inner portions of the signal leads 2B,the wires 4, the support leads 6 and the like are sealed by a resin toform the resin sealer 5. The above steps are shown in FIG. 7(C).

The outer portions of the leads 2 are cut away from the lead body 7 ofthe lead frame LF, the tie bars 8 are cut away from the leads 2, theouter portions of the leads 2 are bent like letter J, and the supportleads 6 are cut away from the lead body 7 of the lead frame LF to almostcomplete the semiconductor device shown in FIG. 1, FIG. 2 and FIG. 3.Thereafter, a temperature cycle test which is an environment test ismade on the semiconductor device and the semiconductor device is shippedas a commercial product. The semiconductor device shipped as acommercial product is mounted on the mounting surface of a packagesubstrate.

As described above, the following effects are obtained according to thisembodiment.

(1) Floating capacitance (parasitic capacitance) applied to the powersupply leads 2A can be made large and floating capacitance applied tothe signal leads 2B can be made small by making the interval L2 betweenthe end portions of the inner portions of the signal leads 2B and thesemiconductor chip 1 larger than the interval L1 between the endportions of the inner portions of the power supply leads 2A and thesemiconductor chip 1, separating the inner portions of the signal leads2B from the main surface of the semiconductor chip 1, and fixing the endportions of the inner portions of the power supply leads 2A to the mainsurface of the semiconductor chip 1. Therefore, the prevention offluctuations in power source potential and the acceleration of thesignal propagation speed can be carried out at the same time. As aresult, the electric characteristics of the semiconductor device can beimproved.

(2) The interval between the end portions of the inner portions of thepower supply leads 2A and the semiconductor chip 1 can be made smallerwhen the end portions of the inner portions of the power supply leads 2Aare fixed to the main surface of the semiconductor chip 1 through theadhesive layer 3 than when the end portions of the inner portions of thepower supply leads 2A are fixed to the main surface of the semiconductorchip 1 through an insulating film. Therefore, floating capacitanceapplied to the power supply leads 2A can be made large.

(3) The cracking of the resin sealer 5 (package cracking) caused by thevaporization and expansion of water absorbed by an insulating film canbe prevented by eliminating the insulating film which easily absorbswater and fixing the end portions of the inner portions of the powersupply leads 2A to the main surface of the semiconductor chip 1.Therefore, the reliability of the semiconductor device can be improved.

In this embodiment, the power supply leads 2A and the signal leads 2Bare formed by bending the end portions of the inner portions. The signalleads 2B may be formed linear without bending. In this case, theinterval L2 between the end portions of the signal leads 2B and thesemiconductor chip 1 can be made much larger than the interval L1between the power supply leads 2A and the semiconductor chip 1, therebymaking it possible to further reduce floating capacitance to be appliedto the signal leads 2B.

In this embodiment, the end portions of the power supply leads 2A arefixed to the main surface of the semiconductor chip 1 through theadhesive layer 3. The end portions of the power supply leads 2A may notbe fixed to the main surface of the semiconductor chip 1. In this case,the support leads 6 are fixed to the main surface or the side surface ofthe semiconductor chip 1.

In this embodiment, the adhesive layer 3 is formed on the chip fixingsurface side of the end portions of the power supply leads 2A in theproduction process of the semiconductor device. The adhesive layer 3 maybe formed in the lead fixing region of the main surface of thesemiconductor chip 1 in the production process of the semiconductordevice.

In this embodiment, the end portions of the power supply leads 2A arefixed to the main surface of the semiconductor chip 1 through theadhesive layer 3. The surface protective film of the semiconductor chip1 may be formed of a multi-layer film including the adhesive layer andthe end portions of the power supply leads 2A may be directly fixed tothe main surface of the semiconductor chip 1.

In this embodiment, the end portions of the signal leads 2B are arrangednear the external terminals BP disposed along the long sides of thesemiconductor chip 1 in the center region of the main surface of thesemiconductor chip 1. The end portions of some signal leads 2B out ofthe plurality of signal leads 2B may be arranged near the long side ofthe semiconductor chip 1 like signal leads 2B1 shown in FIG. 8. In thiscase, the areas opposite to the main surface of the semiconductor chip 1of the signal leads 2B become small, thereby making it possible tofurther reduce floating capacitance (chip/lead capacitance) applied tothe signal leads 2B. This is particularly effective for signal leads 2Bwhich are used as signal terminals such as data input/output terminalsand address terminals.

In this embodiment, the end portions of the signal leads 2B are arrangednear the external terminals BP disposed along the long sides of thesemiconductor chip 1 in the center region of the main surface of thesemiconductor chip 1. Some signal leads 2B out of the plurality ofsignal leads 2B may be arranged outside the periphery of thesemiconductor chip 1 like signal leads 2B1 shown in FIG. 9. In thiscase, the area opposite to the main surface of the semiconductor chip 1can be eliminated, thereby making it possible to further reduce floatingcapacitance (chip/lead capacitance) applied to the signal leads 2B. Thisis particularly effective for signal leads 2B which are used as signalterminals such as data input terminals and address terminals.

In this embodiment, the power supply leads 2A are fixed to the mainsurface of the semiconductor chip 1 to support the semiconductor chip 1.The signal leads which does not require the high signal propagationspeed, for example, signal leads used as a chip select terminal and atesting terminal may be fixed to the main surface of the semiconductorchip 1 to support the semiconductor chip 1.

In this embodiment, the end portions of the inner portions of the powersupply leads 2A are fixed to the main surface of the semiconductor chipthrough the adhesive layer 3. As shown in FIG. 10 and FIG. 11, the endportions of the inner portions of the power supply leads 2A may be fixedto the main surface of the semiconductor chip 1 through an insulatingfilm (insulating tape) 9. The insulating film 9 has an adhesive layerformed of a polyimide-based resin formed on both sides (front side andrear side) of a resin substrate made from a polyimide-based resin. Inthis case, the thickness of the insulating film (including the adhesivelayer) is about 80 μm and the interval between the end portions of thesignal leads 2B and the semiconductor chip 1 is about 100 to 150 μm.

The present invention made by the present inventor has been describedbased on the above embodiment. However, it should be understood that thepresent invention is not limited to the above embodiment and may bemodified and changed without departing from the spirit and scope of theinvention.

For example, the present invention can be applied to an SOP (SmallOut-line Package) or ZIP (Zigzag In-line Package) semiconductor devicewhich is a one-way lead layout structure semiconductor device.

The present invention can be further applied to a DIP (Dual In-linePackage) or TSOP (Thin Small Out-line Package) semiconductor devicewhich is a two-way lead layout structure semiconductor device.

The present invention can be further applied to a QFP (Quad FlatPackage) semiconductor device which is a four-way lead layout structuresemiconductor device.

Industrial Applicability

The electrical characteristics of a semiconductor device can beimproved.

The reliability of a semiconductor device can also be improved.

What is claimed is:
 1. A semiconductor device having power supply leadsand signal leads on the main surface of a semiconductor chip, whereinthe interval between the signal leads and the semiconductor chip is madelarger than the interval between the power supply leads and thesemiconductor chip.
 2. The semiconductor device of claim 1, wherein asurface protective film is formed on the main surface of thesemiconductor chip, and power source wires electrically connected to thepower supply leads are formed under the surface protective film.
 3. Thesemiconductor device of claim 1, wherein the power supply leads and thesignal leads are electrically connected to respective external terminalsarranged on the main surface of the semiconductor chip by wires, thesemiconductor chip, the inner portions of the power supply leads, theinner portions of the signal leads and the wires are sealed by a resinsealer, and the outer portions of the power supply leads and the outerportions of the signal leads are drawn to the outside of the resinsealer.
 4. A semiconductor device having power supply leads and signalleads on the main surface of a semiconductor chip, wherein the intervalbetween the signal leads and the semiconductor chip is made larger thanthe interval between the power supply leads and the semiconductor chip,the signal leads are separated from the main surface of thesemiconductor chip, and the power supply leads are fixed to the mainsurface of the semiconductor chip.
 5. A semiconductor device havingpower supply leads and signal leads on the main surface of asemiconductor chip, wherein the interval between the signal leads andthe semiconductor chip is made larger than the interval between thepower supply leads and the semiconductor chip, the signal leads areseparated from the main surface of the semiconductor chip, and the powersupply leads are fixed to the main surface of the semiconductor chipdirectly or through an adhesive layer.
 6. A semiconductor device havingpower supply leads and signal leads whose end portions are located onthe semiconductor chip side on the main surface of a semiconductor chip,wherein the interval between the end portions of the signal leads andthe semiconductor chip is made larger than the interval between the endportions of the power supply leads and the semiconductor chip.
 7. Thesemiconductor device of claim 6, wherein a surface protective film isformed on the main surface of the semiconductor chip, and power sourcewires electrically connected to the power supply leads are formed underthe surface protective layer.
 8. The semiconductor device of claim 6,wherein the power supply leads and the signal leads are electricallyconnected to respective external terminals arranged on the main surfaceof the semiconductor chip by wires, the semiconductor chip, the innerportions of the power supply leads, the inner portions of the signalleads and the wires are sealed by a resin sealer, and the outer portionsof the power supply leads and the outer portions of the signal leads aredrawn to the outside of the resin sealer.
 9. A semiconductor devicehaving power supply leads and signal leads whose end portions arelocated on the semiconductor chip side on the main surface of asemiconductor chip, wherein the end portions of the signal leads areseparated from the semiconductor chip, and the end portions of the powersupply leads are fixed to the semiconductor chip.
 10. A semiconductordevice having power supply leads and signal leads whose end portions arelocated on the semiconductor chip side on the main surface of asemiconductor chip, wherein the end portions of the signal leads areseparated from the semiconductor chip, and the end portions of the powersupply leads are fixed to the semiconductor chip directly or through anadhesive layer.
 11. A method of manufacturing a semiconductor devicehaving power supply leads and signal leads on the main surface of asemiconductor chip, comprising sealing the semiconductor chip, the innerportions of the power supply leads and the inner portions of the signalleads by a resin while the interval between the signal leads and thesemiconductor chip is made larger than the interval between the powersupply leads and the semiconductor chip, so as to form a resin sealer.12. A method of manufacturing a semiconductor device having power supplyleads and signal leads on the main surface of a semiconductor chip,comprising sealing the semiconductor chip, the inner portions of thepower supply leads and the inner portions of the signal leads by a resinwhile the interval between the signal leads and the semiconductor chipis made larger than the interval between the power supply leads and thesemiconductor chip, the signal leads are separated from thesemiconductor chip, and the power supply leads are fixed to thesemiconductor chip, so as to form a resin sealer.
 13. A method ofmanufacturing a semiconductor device having power supply leads andsignal leads on the main surface of a semiconductor chip, comprisingsealing the semiconductor chip, the inner portions of the power supplyleads and the inner portions of the signal leads by a resin while theinterval between the signal leads and the semiconductor chip is madelarger than the interval between the power supply leads and thesemiconductor chip, the signal leads are separated from thesemiconductor chip, and the power supply leads are fixed to thesemiconductor chip directly or through an adhesive layer, so as to forma resin sealer.
 14. A semiconductor device having power supply leads andsignal leads on the main surface of a semiconductor chip, wherein thesignal leads are separated from the main surface of the semiconductorchip, and the power supply leads are fixed to the main surface of thesemiconductor chip.
 15. A semiconductor device comprising; a rectangularsemiconductor chip having a plurality of semiconductor elements and aplurality of external terminals on the main surface, the plurality ofexternal terminals being arranged in a longitudinal direction; firstleads and second leads, each having inner portions and outer portions,parts of the inner portions being arranged on the main surface of thesemiconductor chip, and the end portions of the inner portions beingarranged near the plurality of external terminals and electricallyconnected to the plurality of external terminals; and a rectangularresin sealer for sealing the semiconductor chip and the inner portionsof the first leads and the second leads, whose long sides extend alongthe long sides of the semiconductor chip and whose short sides extendalong the short sides of the semiconductor chip, wherein the outerportions of the first leads and the second leads project from the longsides of the resin sealer; the inner portions of the first leads and thesecond leads extend over the short sides of the semiconductor chip andlie on the main surface of the semiconductor chip; the distance betweenparts of the inner portions of the second leads lying on the mainsurface of the semiconductor chip and the main surface of thesemiconductor chip is larger than the distance between parts of theinner portions of the first leads lying on the main surface of thesemiconductor chip and the main surface of the semiconductor chip; andthe first leads are connected to fixed potential terminals out of theplurality of external terminals and the second leads are connected tosignal terminals out of the plurality of external terminals.
 16. Thesemiconductor device of claim 15, wherein the first leads and the secondleads are offset such that parts of the inner portions lying on the mainsurface of the semiconductor chip are closer to the main surface of thesemiconductor chip than the other parts of the inner portions lyingoutside the main surface of the semiconductor chip in the vicinity ofthe short sides of the semiconductor chip, and the offset amount of thesecond leads is smaller than the offset amount of the first leads. 17.The semiconductor device of claim 16, wherein parts of the innerportions of the first leads lying on the main surface of thesemiconductor chip are bonded to the main surface of the semiconductorchip.
 18. The semiconductor device of claim 17, wherein parts of theinner portions of the first leads lying on the main surface of thesemiconductor chip are bonded to the main surface of the semiconductorchip by an adhesive.
 19. The semiconductor device of claim 17, whereinparts of the inner portions of the first leads lying on the main surfaceof the semiconductor chip are bonded to the main surface of thesemiconductor chip by an insulating tape.